(1) Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing floating gates, and more particularly, to a method of fabricating memory devices employing trenched floating gates.
(2) Description of the Prior Art
One class of semiconductor memory devices employs floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represents binary information. These are called electrically programmable read only memories (EPROM). EEPROMS are erasable electrically programmable read only memories. A tunneling oxide, necessary for the erase function of the cell, is situated below the floating gate of the memory cell. A large coupling ratio is required to drive electrons through the tunneling oxide. That is, the capacitance between the control gate and the floating gate must be large relative to the capacitance between the floating gate and the channel. In order to achieve a large enough coupling ratio, the floating gate must occupy a large area on the silicon surface.
FIG. 1 illustrates a conventional surface structure floating gate. A thin gate oxide 12 is formed on the surface of a semiconductor substrate 10. N+ regions 14 have been implanted into the semiconductor substrate. A control gate 20 is formed through an opening in the thin oxide layer to contact the N+ region 14. Floating gate 25 is capacitively coupled to the N+ region 14 through the thin gate oxide 12.
It is desired to reduce the surface area of the floating gate in order to fit more devices on the chip. A number of workers in the field have sought to reduce surface area through trenched floating gates of various types. U.S. Pat. No. 5,480,820 to Roth et al shows a floating gate within a trench adjacent to control electrodes alongside the trench. U.S. Pat. No. 5,045,490 to Esquivel et al and U.S. Pat. No. 4,835,741 to Baglee teach a floating gate formed within a trench and a control gate formed within the floating gate. U.S. Pat. No. 5,598,367 to Noble teaches a floating gate within a trench similar to a trenched DRAM cell. U.S. Pat. No. 4,222,062 to Trotter et al discloses a floating gate within a V-shaped trench. U.S. Pat. No. 5,135,879 to Richardson teaches a floating gate formed on the sidewall of a trench.